Processing power of a system can be increased by using multiprocessor systems. Multiprocessing is the use of two or more processors, for example central processing units (CPUs) or microcontrollers, within a single data processing system. A microcontroller incorporates most or all of the functions of a CPU on a single integrated circuit (IC). Instead of using multiple processors or microcontrollers, each with one processor core, a multi-core CPU or multi-core microcontroller, i.e. a chip-level multiprocessor, can be used. A multi-core microprocessor combines two or more independent data processing cores into a single package composed of a single IC, or die, or more dies packaged together.
In a typical multi-core system, all cores are being clocked simultaneously and by the same clock source. The clock rate is the fundamental rate in cycles per second at which a data processing device, for example a processor core, performs its most basic operations such as adding two numbers or transferring a value from one processor register to another. If any erroneous activity causes a disturbance of the clock signal of a multi-core or multiprocessor system, it could have a detrimental effect on the operation of any or all of the cores. Such an effect could be caused by any environmental disturbance, such as noise, radiation, over-voltages, current injection etc., and could have a significant safety implication for the system if any of the cores experience code runaway, for example causing system instability, freezing or failure. In functional safety applications, such as vehicle brake or electrical steering systems, such a malfunction could induce a dangerous situation.
In order to provide a reliable clock signal for clocking multiple data processing devices, two redundant sources of clock generation can be used, as described in “Fully redundant clock generation and distribution with dynamic oscillator switchover”, IBM System z9, volume 51, number 1/2, 2007. However, both clocks can be disturbed by the same event, since some elements of the system are shared. Other systems, such as the system described in document U.S. Pat. No. 6,920,572 B2, use the same clock source but comprise a clock tree that distributes clock signals to processor cores and a common shared component. The clock tree can be configured to disable one or more of the processor cores and shared component by blocking the corresponding clock signal. The clock signal for the shared component is preserved until the shared component is disabled by all of the processor cores. Therefore, one disturbance event can still affect the clock to multiple cores since some elements, such as power supply, are shared.
It is also possible to dedicate additional circuitry to the monitoring of possible sources of disturbance, for example the power noise a microcontroller encounters, and to reset, freeze or stop the system in order to preserve it from malfunction, as described in “Design of a noise-free microcontroller”, Hyundai Electron. Co. Ltd., ISBN: 0-7803-6470-8. Freezing a clocked device refers to providing the device with no or a constant clock signal having no signal changes from low to high or vice versa, causing the device to preserve the last state of processing, for example contents of registers and logic circuitry, until a next clock edge continues triggering the data processing.